WHL holds 25 filed provisional patents under USPTO 19/567,170, with 5 additional bundles drafted and ready for attorney review. Every patent maps to a layer of the governed execution stack.
Filed under USPTO Application 19/567,170. Each patent covers a discrete layer of the governed execution stack, from waveform-level enforcement to OS-level state-machine governance. Crown jewels are marked with a star.
| # | Title | Status |
|---|---|---|
| P1 | Governance Architecture (Proposal vs Execution) | Filed |
| P2 | Genesis Root (Quantum-Temporal Logic) | Filed |
| P3 | Sovereign Arbiter / HW Signal Coherence Interlock | Filed |
| P4 | Resilient Orchestration (Rollback / Substitution) | Filed |
| ★ P5 | DSP Action Waveform Enforcement Crown Jewel | Filed |
| P6 | Loopback Attestation (Hardware via Audio Correlation) | Filed |
| ★ P7 | Analog Mixer Physical Authorization Crown Jewel | Filed |
| ★ P8 | Governed Execution OS (GE-OS) Crown Jewel | Filed |
| P9 | Temporal Authorization (Anti-Replay) | Filed |
| P10 | Hierarchical Authorization + Physical Attestation | Filed |
| P11 | Continuous Spectral Integrity Verification | Filed |
| ★ P12 | Deterministic State Machine Governance Crown Jewel | Filed |
| P13 | Multi-Layer Defense Through Signal Diversity | Filed |
| P14 | Authorization Path Reconstitution Fail-Closed | Filed |
| P15 | Quantum-Resistant Physical Authentication (PUF) | Filed |
| P16 | Adaptive Threshold Calibration with ML | Filed |
| P17 | Hardware-Anchored Thermodynamic Governance | Filed |
| P18 | Geometric Coherence & Stability (CSEL) | Filed |
| ★ P19 | Thermodynamic Training Loss Crown Jewel | Filed |
| ★ P20 | HW-Bound Crypto Licensing (CSEL Hypervisor) Crown Jewel | Filed |
| P21 | Predictive Entropy Trading / Geometric Black Box | Filed |
| P22 | Governed WPT 6-Gate Admissibility | Possibly Filed (Patent Center verification pending) |
| P23 | GCMP Hardened (Cognitive-Motor Pipeline) | Filed |
| P24 | Fault-Injection-Resilient Interlock | Filed |
| P25 | Dual-Control Scope-Limited Human-in-the-Loop | Filed |
The strategic core of the portfolio. These patents establish the foundation for governed execution from waveform-level signal enforcement up through OS-level state-machine governance. All filed under USPTO 19/567,170.
Action authorization expressed as a DSP-enforced waveform, any execution path whose signal signature drifts from the authorized template is rejected at the physical layer before reaching the actuator.
Filed under USPTO 19/567,170
Physical authorization via analog signal mixing, only the correct combination of analog reference signals produces the demodulated authorization token, making bypass physically rather than computationally hard.
Filed under USPTO 19/567,170
A full operating-system architecture where every execution path passes through a 12-stage governance pipeline before reaching any actuator, with hardware-rooted attestation at every boundary. Sole-source SBIR Phase III transition pathway available.
Filed under USPTO 19/567,170
Governance expressed as a deterministic finite-state machine, every legal transition is enumerated, signed, and replayable. Non-enumerated transitions are physically unreachable, eliminating an entire class of authorization-bypass attacks.
Filed under USPTO 19/567,170
A training objective that incorporates a thermodynamic-loss term, producing models whose internal energy gradients are bounded and whose drift behavior is provably constrained, relevant to AI safety, drift monitoring, and provable training receipts.
Filed under USPTO 19/567,170
A hypervisor-class containment layer that binds cryptographic licensing to specific hardware silicon, software cannot execute outside the authorized physical envelope, enabling provable per-device licensing for AI weights, firmware, and regulated code.
Filed under USPTO 19/567,170
Drafted and ready for attorney review. Each bundle covers a distinct invention family with multiple independent and dependent claims, sourced from working code in the governed execution stack.
Covers Codex Sovereign, a domain-specific language whose source instructions compile through a deterministic governance kernel and emit to multiple execution targets (FPGA frames, REST endpoints, mesh transport, FSM transitions) with byte-identical authorization.
A 9-field execution signature with a 500ms–2s predictive horizon for detecting GPU scheduler interference and tail-latency drift. Includes perceptual stutter thresholds and timer-tick reconstruction. Prioritized for first filing.
Drift detection over the geometry of system state graphs, paired with adaptive control law. Enables provable bounds on configuration drift and a deterministic rejection criterion for proposals that exceed calibrated thresholds.
An ensemble of 22 spectral-governance modules operating as a dual-force balancing engine. Includes phi-weighted quantum-fidelity metrics, lattice-based routing maps, and minimum-intervention stability thresholds. The ensemble claim covers all 22 modules as a unified inventive concept.
A 75/25 nickel-chromium alloy with ±100 ppm chromium tolerance, used as a composition-bound Hardware Root of Trust. The shield's measured EMI signature serves as an attestation primitive; manufacturing tolerance is the cryptographic binding.
The 25 filed provisionals expire on a rolling schedule across January and February 2027. The conversion plan consolidates families into three coordinated non-provisional applications.
Jan 26–28, 2027, P1 through P12 expire.
Feb 4, 2027, P19, P20, and P22 expire.
Feb 6, 2027, P25 expires.
New drafted bundles, once filed, will set their own 12-month conversion windows.
NP-Alpha, Bundle 1 (Symbolic-DSL) + Bundle 4 (Spectral Dual-Force Ensemble).
NP-Beta, Bundle 2 (GPU Tail-Latency) standalone.
NP-Gamma, Bundle 3 (Ricci-Curvature) + Bundle 5 (NiCr Shield), conditional on technical and regulatory review.
We license individual patents, patent families, and the entire IP portfolio. NDA-bound briefings for strategic acquirers, defense primes, and regulated-enterprise integrators.